View LTC2170IUKG-14PBF_6735039.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ltc2172-14/ ltc2171-14/ltc2170-14 1 21721014fb typical a pplica t ion descrip t ion 14-bit, 65msps/40msps/ 25msps low power quad adcs the lt c ? 2172-14/ltc2171-14/ltc2170-14 are 4-channel, simultaneous sampling 14- bit a/d converters designed for digitizing high frequency, wide dynamic range signals. they are perfect for demanding communications applications with ac performance that includes 73.7 db snr and 90db spurious free dynamic range ( sfdr). an ultralow jitter of 0.15ps rms allows undersampling of if frequencies with excellent noise performance. dc specifications include 1 lsb inl (typ), 0.3 lsb dnl (typ) and no missing codes over temperature. the transi- tion noise is a low 1.2lsb rms . the digital outputs are serial lvds to minimize the num- ber of data lines. each channel outputs two bits at a time (2-lane mode) or one bit at a time (1- lane mode). the lvds drivers have optional internal termination and adjustable output levels to ensure clean signal integrity. the enc + and enc C inputs may be driven differentially or single-ended with a sine wave, pecl, lvds, ttl or cmos inputs. an internal clock duty cycle stabilizer al- lows high performance at full speed for a wide range of clock duty cycles. ltc2172-14, 65msps, 2-tone fft , f in = 70mhz and 75mhz fea t ures a pplica t ions n 4-channel simultaneous sampling adc n 73.7db snr n 90db sfdr n low power: 311mw/202mw/162mw total, 78mw/51mw/41mw per channel n single 1.8v supply n serial lvds outputs: one or tw o bits per channel n selectable input ranges: 1v p-p to 2v p-p n 800mhz full power bandwidth sample-and-hold n shutdown and nap modes n serial spi port for configuration n pin-compatible 14-bit and 12-bit versions n 52-pin (7mm 8mm) qfn package n communications n cellular base stations n software defined radios n portable medical imaging n multichannel data acquisition n nondestructive t esting l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. data serializer encode input serialized lvds outputs 1.8v v dd 1.8v ov dd out1a out1b out2a out2b out3a out3b out4a out4b data clock out frame ognd gnd 217214 ta01 s/h channel 1 analog input 14-bit adc core s/h channel 2 analog input 14-bit adc core s/h channel 3 analog input 14-bit adc core s/h channel 4 analog input 14-bit adc core pll frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 217214 ta01b
ltc2172-14/ ltc2171-14/ltc2170-14 2 21721014fb p in c on f igura t ion a bsolu t e maxi m u m r a t ings supply voltages v dd , ov dd ............................................... C0.3 v to 2v analog input voltage (a in + , a in C , par / ser , sense ) ( note 3) .......... C 0.3 v to (v dd + 0.2 v) digital input voltage ( enc + , enc C , cs , sdi , sck ) ( note 4) .................................... C 0.3 v to 3.9 v sdo ( note 4) ............................................. C 0.3 v to 3.9 v digital output voltage ................ C 0.3 v to ( ov dd + 0.3 v) operating temperature range ltc 2 172 c, ltc 2171 c, ltc 2170 c ............. 0 c to 70 c ltc 2 172 i, ltc 2171 i, ltc 2170 i ............ C 40 c to 85 c storage temperature range .................. C 65 c to 150 c (notes 1 and 2) 16 15 17 18 19 top view 53 gnd ukg package 52-lead (7mm 8mm) plastic qfn 20 21 22 23 24 25 26 51 52 50 49 48 47 46 45 44 43 42 41 33 34 35 36 37 38 39 40 8 7 6 5 4 3 2 1a in1 + a in1 ? v cm12 a in2 + a in2 ? refh refh refl refl a in3 + a in3 ? v cm34 a in4 + a in4 ? out2a + out2a ? out2b + out2b ? dco + dco ? ov dd ognd fr + fr ? out3a + out3a ? out3b + out3b ? v dd v dd sense gnd v ref par/ ser sdo gnd out1a + out1a ? out1b + out1b ? v dd v dd enc + enc ? cs sck sdi gnd out4b ? out4b + out4a ? out4a + 32 31 30 29 28 27 9 10 11 12 13 14 t jmax = 150c, ja = 28c/w exposed pad (pin 53) is gnd, must be soldered to pcb o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc2172cukg-14#pbf ltc2172cukg-14#trpbf ltc2172ukg-14 52-lead (7mm 8mm) plastic qfn 0c to 70c ltc2172iukg-14#pbf ltc2172iukg-14#trpbf ltc2172ukg-14 52-lead (7mm 8mm) plastic qfn C40c to 85c ltc2171cukg-14#pbf ltc2171cukg-14#trpbf ltc2171ukg-14 52-lead (7mm 8mm) plastic qfn 0c to 70c ltc2171iukg-14#pbf ltc2171iukg-14#trpbf ltc2171ukg-14 52-lead (7mm 8mm) plastic qfn C40c to 85c ltc2170cukg-14#pbf ltc2170cukg-14#trpbf ltc2170ukg-14 52-lead (7mm 8mm) plastic qfn 0c to 70c ltc2170iukg-14#pbf ltc2170iukg-14#trpbf ltc2170ukg-14 52-lead (7mm 8mm) plastic qfn C40c to 85c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ltc2172-14/ ltc2171-14/ltc2170-14 3 21721014fb c onver t er c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) parameter conditions ltc2172-14 ltc2171-14 ltc2170-14 units min typ max min typ max min typ max resolution ( no missing codes) l 14 14 14 bits integral linearity error differential analog input (note 6) l C3.25 1 3.25 C2.75 1 2.75 C2.75 1 2.75 lsb differential linearity error differential analog input l C0.8 0.3 0.8 C0.8 0.3 0.8 C0.8 0.3 0.8 lsb offset error (note 7) l C12 3 12 C12 3 12 C12 3 12 mv gain error internal reference external reference l C2.5 C1 C1 0.5 C2.5 C1 C1 0.5 C2.5 C1 C1 0.5 %fs %fs offset drift 20 20 20 v/c full-scale drift internal reference external reference 35 25 35 25 35 25 ppm/c ppm/c gain matching external reference 0.2 0.2 0.2 %fs offset matching 3 3 3 mv transition noise external reference 1.2 1.2 1.2 lsb rms a nalog i npu t the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units v in analog input range (a in + C a in C ) 1.7v < v dd < 1.9v l 1 to 2 v p-p v in(cm) analog input common mode (a in + + a in C )/2 differential analog input (note 8) l v cm C 100 mv v cm v cm + 100mv v v sense external voltage reference applied to sense external reference mode l 0.625 1.250 1.300 v i in(cm) analog input common mode current per pin, 65msps per pin, 40msps per pin, 25msps 81 50 31 a a a i in1 analog input leakage current (no encode) 0 < a in + , a in C < v dd l C1 1 a i in2 par /ser input leakage current 0 < par /ser < v dd l C3 3 a i in3 sense input leakage current 0.625 < sense < 1.3v l C6 6 a t ap sample-and-hold acquisition delay time 0 ns t jitter sample-and-hold acquisition delay jitter 0.15 ps rms cmrr analog input common mode rejection ratio 80 db bw-3b full-power bandwidth figure 6 test circuit 800 mhz
ltc2172-14/ ltc2171-14/ltc2170-14 4 21721014fb dyna m ic a ccuracy the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. a in = C1dbfs. (note 5) symbol parameter conditions ltc2172-14 ltc2171-14 ltc2170-14 units min typ max min typ max min typ max snr signal-to-noise ratio 5mhz input 30mhz input 70mhz input 140mhz input l 72.0 73.7 73.7 73.5 73 71.7 73.5 73.4 73.4 72.8 71.1 72.9 72.9 72.8 72.3 dbfs dbfs dbfs dbfs sfdr spurious free dynamic range 2nd or 3rd harmonic 5mhz input 30mhz input 70mhz input 140mhz input l 77 90 90 89 84 80 90 90 89 84 80 90 90 89 84 dbfs dbfs dbfs dbfs spurious free dynamic range 4th harmonic or higher 5mhz input 30mhz input 70mhz input 140mhz input l 85 90 90 90 90 85 90 90 90 90 85 90 90 90 90 dbfs dbfs dbfs dbfs s/(n+d) signal-to-noise plus distortion ratio 5mhz input 30mhz input 70mhz input 140mhz input l 71.2 73.6 73.5 73.2 72.5 71.3 73.3 73.2 73.1 72.3 70.8 72.8 72.7 72.5 71.9 dbfs dbfs dbfs dbfs crosstalk, near channel 10mhz input (note 12) C90 C90 C90 dbc crosstalk, far channel 10mhz input (note 12) C105 C105 C105 dbc i n t ernal r e f erence c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. a in = C1dbfs. (note 5) parameter conditions min typ max units v cm output voltage i out = 0 0.5 ? v dd C 25mv 0.5 ? v dd 0.5 ? v dd + 25mv v v cm output temperature drift 25 ppm/c v cm output resistance C600a < i out < 1ma 4 v ref output voltage i out = 0 1.225 1.250 1.275 v v ref output temperature drift 25 ppm/c v ref output resistance C400a < i out < 1ma 7 v ref line regulation 1.7v < v dd < 1.9v 0.6 mv/v
ltc2172-14/ ltc2171-14/ltc2170-14 5 21721014fb symbol parameter conditions min typ max units encode inputs (enc + , enc C ) differential encode mode (enc C not tied to gnd) v id differential input voltage (note 8) l 0.2 v v icm common mode input voltage internally set externally set (note 8) l 1.1 1.2 1.6 v v v in input voltage range enc + , enc C to gnd l 0.2 3.6 v r in input resistance (see figure 10) 10 k c in input capacitance 3.5 pf single-ended encode mode (enc C tied to gnd) v ih high level input voltage v dd = 1.8v l 1.2 v v il low level input voltage v dd = 1.8v l 0.6 v v in input voltage range enc + to gnd l 0 3.6 v r in input resistance (see figure 11) 30 k c in input capacitance 3.5 pf digital inputs ( cs, sdi, sck in serial or parallel programming mode. sdo in parallel programming mode) v ih high level input voltage v dd = 1.8v l 1.3 v v il low level input voltage v dd = 1.8v l 0.6 v i in input current v in = 0v to 3.6v l C10 10 a c in input capacitance 3 pf sdo output (serial programming mode. open-drain output. requires 2k pull-up resistor if sdo is used) r ol logic low output resistance to gnd v dd = 1.8v, sdo = 0v 200 i oh logic high output leakage current sdo = 0v to 3.6v l C10 10 a c out output capacitance 3 pf digital d ata outputs v od differential output voltage 100 differential load, 3.5ma mode 100 differential load, 1.75ma mode l l 247 125 350 175 454 250 mv mv v os common mode output voltage 100 differential load, 3.5ma mode 100 differential load, 1.75ma mode l l 1.125 1.125 1.250 1.250 1.375 1.375 v v r term on-chip termination resistance termination enabled, ov dd = 1.8v 100 digi t al i npu t s a n d o u t pu t s the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5)
ltc2172-14/ ltc2171-14/ltc2170-14 6 21721014fb ti m ing c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions ltc2172-14 ltc2171-14 ltc2170-14 units min typ max min typ max min typ max f s sampling frequency (notes 10, 11) l 5 65 5 40 5 25 mhz t encl enc low time (note 8) duty cycle stabilizer off duty cycle stabilizer on l l 7.3 2 7.69 7.69 100 100 11.88 2 12.5 12.5 100 100 19 2 20 20 100 100 ns ns t ench enc high time (note 8) duty cycle stabilizer off duty cycle stabilizer on l l 7.3 2 7.69 7.69 100 100 11.88 2 12.5 12.5 100 100 19 2 20 20 100 100 ns ns t ap sample-and-hold acquisition delay time 0 0 0 ns p ower r equire m en t s the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 9) symbol parameter conditions ltc2172-14 ltc2171-14 ltc2170-14 units min typ max min typ max min typ max v dd analog supply voltage (note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v ov dd output supply voltage (note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v i vdd analog supply current sine wave input l 157 181 96 112 75 85 ma i ovdd digital supply current 1-lane mode, 1.75ma mode 1-lane mode, 3.5ma mode 2-lane mode, 1.75ma mode 2-lane mode, 3.5ma mode l l 16 30 25 47 29 52 16 29 24 46 27 51 15 28 24 45 27 50 ma ma ma ma p diss power dissipation 1-lane mode, 1.75ma mode 1-lane mode, 3.5ma mode 2-lane mode, 1.75ma mode 2-lane mode, 3.5ma mode l l 311 337 328 367 378 419 202 225 216 256 250 293 162 185 178 216 202 243 mw mw mw mw p sleep sleep mode power 1 1 1 mw p nap nap mode power 75 75 75 mw p diffclk power increase with differential encode mode enabled (no increase for sleep mode) 20 20 20 mw
ltc2172-14/ ltc2171-14/ltc2170-14 7 21721014fb symbol parameter conditions min typ max units digital data outputs (r term = 100 differential, c l = 2pf to gnd on each output) t ser serial data bit period 2-lanes, 16-bit serialization 2-lanes, 14-bit serialization 2-lanes, 12-bit serialization 1-lane, 16-bit serialization 1-lane, 14-bit serialization 1-lane, 12-bit serialization 1 / (8 ? f s ) 1 / (7 ? f s ) 1 / (6 ? f s ) 1 / (16 ? f s ) 1 / (14 ? f s ) 1 / (12 ? f s ) s s s s s s t frame fr to dco delay (note 8) l 0.35 ? t ser 0.5 ? t ser 0.65 ? t ser s t data data to dco delay (note 8) l 0.35 ? t ser 0.5 ? t ser 0.65 ? t ser s t pd propagation delay (note 8) l 0.7n + 2 ? t ser 1.1n + 2 ? t ser 1.5n + 2 ? t ser s t r output rise time data, dco, fr, 20% to 80% 0.17 ns t f output fall time data, dco, fr, 20% to 80% 0.17 ns dco cycle-to-cycle jitter t ser = 1ns 60 ps p-p pipeline latency 6 cycles spi port timing (note 8) t sck sck period write mode readback mode, c sdo = 20pf, r pullup = 2k l l 40 250 ns ns t s cs to sck set-up time l 5 ns t h sck to cs set-up time l 5 ns t ds sdi set-up time l 5 ns t dh sdi hold time l 5 ns t do sck falling to sdo valid readback mode c sdo = 20pf, r pullup = 2k l 125 ns note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd with gnd and ognd shorted (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: when these pin voltages are taken below gnd they will be clamped by internal diodes. when these pin voltages are taken above v dd they will not be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd without latchup. note 5: v dd = ov dd = 1.8v, f sample = 65mhz (ltc2172), 40mhz (ltc2171), or 25mhz (ltc2170), 2-lane output mode, differential enc + /enc C = 2v p-p sine wave, input range = 2v p-p with differential drive, unless otherwise noted. note 6: integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. the deviation is measured from the center of the quantization band. note 7: offset error is the offset voltage measured from C0.5 lsb when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111 in 2s complement output mode. note 8: guaranteed by design, not subject to test. note 9: v dd = ov dd = 1.8v, f sample = 65mhz (ltc2172), 40mhz (ltc2171), or 25mhz (ltc2170), 2-lane output mode, enc + = single- ended 1.8v square wave, enc C = 0v, input range = 2v p-p with differential drive, unless otherwise noted. the supply current and power dissipation specifications are totals for the entire chip, not per channel. note 10: recommended operating conditions. note 11: the maximum sampling frequency depends on the speed grade of the part and also which serialization mode is used. the maximum serial data rate is 1000mbps, so t ser must be greater than or equal to 1ns. note 12: near-channel crosstalk refers to ch. 1 to ch.2, and ch.3 to ch.4. far- channel crosstalk refers to ch.1 to ch.3, ch.1 to ch.4, ch.2 to ch.3, and ch.2 to ch.4. t i m ing charac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5)
ltc2172-14/ ltc2171-14/ltc2170-14 8 21721014fb ti m ing diagra m s 2-lane output mode, 16-bit serialization* 2-lane output mode, 14-bit serialization 217214 td01 t ap n + 1 n analog input enc ? dco ? fr ? enc + dco + fr + out#a + *see the digital outputs section sample n-6 sample n-5 out#a ? out#b + out#b ? sample n-4 t frame t data t ser t ser t pd d5 d3 d1 0 d13 d11 d9 d7 d5 d3 d1 0 d13 d11 d9 d4 d2 d0 0 d12 d10 d8 d6 d4 d2 d0 0 d12 d10 d8 t ench t encl t ser 217214 td02 t ap n + 2 n + 1 n analog input enc ? dco ? fr ? enc + dco + fr + out#a + note that in this mode, fr + /fr ? has two times the period of enc + /enc ? sample n-6 sample n-5 out#a ? out#b + out#b ? sample n-3 sample n-4 t frame t data t ser t ser t pd d7 d5 d3 d1 d13 d11 d9 d7 d5 d3 d1 d13 d11 d9 d7 d5 d3 d1 d13 d11 d9 d6 d4 d2 d0 d12 d10 d8 d6 d4 d2 d0 d12 d10 d8 d6 d4 d2 d0 d12 d10 d8 t ench t encl t ser
ltc2172-14/ ltc2171-14/ltc2170-14 9 21721014fb t i m ing d iagra m s 2-lane output mode, 12-bit serialization 1-lane output mode, 16-bit serialization 217214 td04 t ap n + 1 n analog input enc ? dco ? fr ? enc + dco + fr + out#a + out#b + , out#b ? are disabled sample n-6 sample n-5 sample n-4 out#a ? t frame t data t ser t ser t pd d1 d0 0 0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 d13 d12 d11 d10 t ench t encl t ser 217214 td03 t ap n + 1 n analog input enc ? dco ? fr + enc + dco + fr ? out#a + sample n-6 sample n-5 out#a ? out#b + out#b ? sample n-4 t frame t data t ser t ser t pd d9 d7 d5 d3 d13 d11 d9 d7 d5 d3 d13 d11 d9 d8 d6 d4 d2 d12 d10 d8 d6 d4 d2 d12 d10 d8 t ench t encl t ser
ltc2172-14/ ltc2171-14/ltc2170-14 10 21721014fb 217214 td05 t ap n + 1 n analog input enc ? dco ? fr ? enc + dco + fr + out#a + out#b + , out#b ? are disabled sample n-6 sample n-5 sample n-4 out#a ? t frame t data t ser t ser t pd d3 d2 d1 d0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d13 d12 d11 d10 t ench t encl t ser t i m ing d iagra m s 1-lane output mode, 14-bit serialization 1-lane output mode, 12-bit serialization 217214 td06 t ap n + 1 n analog input enc ? dco ? fr ? enc + dco + fr + out#a + out#b + , out#b ? are disabled sample n-6 sample n-5 sample n-4 out#a ? t frame t data t ser t ser t pd d5 d4 d3 d2 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d13 d12 d11 t ench t encl t ser
ltc2172-14/ ltc2171-14/ltc2170-14 11 21721014fb spi port timing (readback mode) a6 t s t ds a5 a4 a3 a2 a1 a0 xx d7 d6 d5 d4 d3 d2 d1 d0 xx xx xx xx xx xx xx cs sck sdi r/w sdo high impedance t dh t do t sck t h a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 217214 td07 cs sck sdi r/w sdo high impedance spi port timing (write mode) t i m ing d iagra m s
ltc2172-14/ ltc2171-14/ltc2170-14 12 21721014fb ltc2172-14: 8k point fft , f in = 30mhz, C1dbfs, 65msps ltc2172-14: 8k point fft , f in = 70mhz, C1dbfs, 65msps ltc2172-14: 8k point fft , f in = 140mhz, C1dbfs, 65msps ltc2172-14: 8k point 2-tone fft , f in = 68mhz, 69mhz, C1dbfs, 65msps ltc2172-14: shorted input histogram ltc2172-14: snr vs input frequency, C1dbfs, 2v range, 65msps ltc2172-14: integral nonlinearity (inl) ltc2172-14: differential nonlinearity (dnl) ltc2172-14: 8k point fft , f in = 5mhz, C1dbfs, 65msps typical p er f or m ance c harac t eris t ics frequency (mhz) ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 217214 g03 0 10 20 30 output code 0 ?2.0 ?0.5 ?1.0 ?1.5 inl error (lsb) 0 0.5 1.0 1.5 2.0 4096 8192 12288 16384 217214 g01 output code 0 ?1.0 ?0.4 ?0.2 ?0.6 ?0.8 dnl error (lsb) 0 0.4 0.2 0.6 0.8 1.0 4096 8192 12288 16384 217214 g02 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 217214 g04 10 20 30 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 217214 g05 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 217214 g06 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 217214 g07 output code 8197 1000 0 3000 2000 count 4000 5000 6000 8199 8201 8203 8205 217214 g08 input frequency (mhz) 0 72 71 70 69 68 67 66 74 73 snr (dbfs) 50 100 150 200 250 300 350 217214 g09
ltc2172-14/ ltc2171-14/ltc2170-14 13 21721014fb i ovdd vs sample rate, 5mhz sine wave input, C1dbfs ltc2172-14: snr vs sense, f in = 5mhz, C1dbfs ltc2171-14: integral nonlinearity (inl) ltc2171-14: differential nonlinearity (dnl) ltc2171-14: 8k point fft , f in = 5mhz C1dbfs, 40msps ltc2172-14: sfdr vs input level, f in = 70mhz, 2v range, 65msps ltc2172-14: ivdd vs sample rate, 5mhz sine wave input, C1dbfs ltc2172-14: sfdr vs input frequency, C1dbfs, 2v range, 65msps typical p er f or m ance c harac t eris t ics input frequency (mhz) 0 90 85 80 75 70 65 95 sfdr (dbfs) 50 100 150 200 250 300 350 217214 g10 input level (dbfs) ?80 60 50 40 30 20 10 0 80 70 sfdr (dbc and dbfs) 90 100 110 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 217214 g11 dbfs dbc sense pin (v) 0.6 72 69 70 71 68 67 73 74 75 snr (dbfs) 0.7 0.8 0.9 1.1 1.2 1.3 1 217214 g14 output code 0 ?2.0 ?0.5 ?1.0 ?1.5 inl error (lsb) 0 0.5 1.0 1.5 2.0 4096 8192 12288 16384 217214 g15 output code 0 ?1.0 ?0.4 ?0.2 ?0.6 ?0.8 dnl error (lsb) 0 0.4 0.2 0.6 0.8 1.0 4096 8192 12288 16384 217214 g16 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 217214 g17 input level (dbfs) 60 50 40 30 20 10 0 80 70 snr (dbc and dbfs) ?60 ?50 ?40 ?30 ?20 ?10 0 217214 g50 dbc dbfs sample rate (msps) 160 155 150 145 140 135 130 125 120 115 110 i vdd (ma) 0 10 20 30 40 50 60 217214 g53 sample rate (msps) 50 40 30 20 10 0 io vdd (ma) 0 20 40 60 217214 g51 1-lane, 1.75ma 2-lane, 3.5ma 2-lane, 1.75ma 1-lane, 3.5ma ltc2172-14: snr vs input level, f in = 70mhz, 2v range, 65msps
ltc2172-14/ ltc2171-14/ltc2170-14 14 21721014fb typical p er f or m ance c harac t eris t ics ltc2171-14: 8k point fft , f in = 69mhz, C1dbfs, 40msps ltc2171-14: 8k point fft , f in = 139mhz, C1dbfs, 40msps ltc2171-14: 8k point 2-tone fft , f in = 68mhz, 69mhz, C1dbfs, 40msps ltc2171-14: i vdd vs sample rate, 5mhz sine wave input, C1dbfs ltc2171-14: shorted input histogram ltc2171-14: sfdr vs input level, f in = 70mhz, 2v range, 40msps ltc2171-14: snr vs input frequency, C1dbfs, 2v range, 40msps ltc2171-14: sfdr vs input frequency, C1dbfs, 2v range, 40msps frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 217214 g19 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 217214 g20 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 217214 g21 output code 8198 1000 0 3000 2000 count 4000 5000 6000 8200 8202 8204 8206 217214 g22 input frequency (mhz) 0 72 71 70 69 68 67 66 74 73 snr (dbfs) 50 100 150 200 250 300 350 217214 g23 input frequency (mhz) 0 90 85 80 75 70 65 95 sfdr (dbfs) 50 100 150 200 250 300 350 217214 g24 input level (dbfs) ?80 60 50 40 30 20 10 0 80 70 sfdr (dbc and dbfs) 90 100 110 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 217214 g25 dbfs dbc sample rate (msps) 100 95 90 85 80 75 70 i vdd (ma) 0 10 20 30 40 217214 g54 ltc2171-14: 8k point fft , f in = 29mhz, C1dbfs, 40msps frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 217214 g18
ltc2172-14/ ltc2171-14/ltc2170-14 15 21721014fb ltc2171-14: snr vs sense, f in = 5mhz, C1dbfs ltc2170-14: integral nonlinearity (inl) ltc2170-14: differential nonlinearity (dnl) ltc2170-14: 8k point fft , f in = 5mhz C1dbfs, 25msps ltc2170-14: 8k point fft , f in = 30mhz C1dbfs, 25msps ltc2170-14: 8k point fft , f in = 70mhz C1dbfs, 25msps ltc2170-14: 8k point fft , f in = 140mhz C1dbfs, 25msps ltc2170-14: 8k point 2-tone fft , f in = 68mhz, 69mhz, C1dbfs, 25msps ltc2170-14: shorted input histogram typical p er f or m ance c harac t eris t ics sense pin (v) 0.6 71 68 69 70 67 66 72 73 74 snr (dbfs) 0.7 0.8 0.9 1.1 1.2 1.3 1 217214 g27 output code 0 ?2.0 ?0.5 ?1.0 ?1.5 inl error (lsb) 0 0.5 1.0 1.5 2.0 4096 8192 12288 16384 217214 g28 output code 0 ?1.0 ?0.4 ?0.2 ?0.6 ?0.8 dnl error (lsb) 0 0.4 0.2 0.6 0.8 1.0 4096 8192 12288 16384 217214 g29 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 5 10 217214 g30 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 5 10 217214 g31 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 5 10 217214 g32 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 5 10 217214 g33 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 5 10 217214 g34 output code 8198 1000 0 3000 2000 count 4000 5000 6000 8200 8202 8204 8206 217214 g35
ltc2172-14/ ltc2171-14/ltc2170-14 16 21721014fb input frequency (mhz) 0 90 85 80 75 70 65 95 sfdr (dbfs) 50 100 150 200 250 300 350 217214 g37 input level (dbfs) ?80 60 50 40 30 20 10 0 80 70 sfdr (dbc and dbfs) 90 100 110 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 217214 g38 dbfs dbc sense pin (v) 0.6 71 68 69 70 67 66 72 73 74 snr (dbfs) 0.7 0.8 0.9 1.1 1.2 1.3 1 217214 g40 ltc2170-14: sfdr vs input level, f in = 70mhz, 2v range, 25msps ltc2170-14: sfdr vs input frequency, C1dbfs, 2v range, 25msps ltc2170-14: i vdd vs sample rate, 5mhz sine wave input, C1dbfs ltc2170-14: snr vs sense, f in = 5mhz, C1dbfs typical p er f or m ance c harac t eris t ics ltc2170-14: snr vs input frequency, C1dbfs, 2v range, 25msps input frequency (mhz) 0 72 71 70 69 68 67 66 74 73 snr (dbfs) 50 100 150 200 250 300 350 217214 g36 serial data rate (mbps) 350 300 250 200 150 100 50 0 peak-to-peak jitter (ps) 0 200 400 600 800 1000 217214 g52 sample rate (msps) 80 75 70 65 60 i vdd (ma) 0 5 10 15 2520 217214 g55 dco cycle-cycle jitter vs serial data rate
ltc2172-14/ ltc2171-14/ltc2170-14 17 21721014fb a in1 + (pin 1): channel 1 positive differential analog input. a in1 C ( pin 2): channel 1 negative differential analog input. v cm12 (pin 3): common mode bias output, nominally equal to v dd /2. v cm should be used to bias the common mode of the analog inputs of channels 1 and 2. bypass to ground with a 0.1f ceramic capacitor. a in2 + (pin 4): channel 2 positive differential analog input. a in2 C ( pin 5): channel 2 negative differential analog input. refh (pins 6, 7): adc high reference. bypass to pin 8 and pin 9 with a 2.2 f ceramic capacitor, and to ground with a 0.1f ceramic capacitor. refl (pins 8, 9): adc low reference. bypass to pin 6 and pin 7 with a 2.2 f ceramic capacitor, and to ground with a 0.1f ceramic capacitor. a in3 + (pin 10): channel 3 positive differential analog input. a in3 C (pin 11): channel 3 negative differential analog input. v cm34 ( pin 12): common mode bias output, nominally equal to v dd /2. v cm should be used to bias the common mode of the analog inputs of channels 3 and 4. bypass to ground with a 0.1f ceramic capacitor. a in4 + (pin 13): channel 4 positive differential analog input. a in4 C (pin 14): channel 4 negative differential analog input. v dd (pins 15, 16, 51, 52): 1.8 v analog power supply. bypass to ground with 0.1 f ceramic capacitors. adjacent pins can share a bypass capacitor. enc + (pin 17): encode input. conversion starts on the rising edge. enc C (pin 18): encode complement input. conversion starts on the falling edge. cs (pin 19): in serial programming mode ( par /ser = 0v), cs is the serial interface chip select input. when cs is low, sck is enabled for shifting data on sdi into the mode control registers. in parallel programming mode ( par / ser = v dd ), cs selects two-lane or one-lane output mode. cs can be driven with 1.8v to 3.3v logic. sck (pin 20): in serial programming mode ( par /ser = 0 v), sck is the serial interface clock input. in parallel programming mode ( par /ser = v dd ), sck selects 3.5ma or 1.75 ma lvds output currents. sck can be driven with 1.8v to 3.3v logic. sdi (pin 21): in serial programming mode ( par /ser = 0v), sdi is the serial interface data input. data on sdi is clocked into the mode control registers on the rising edge of sck. in parallel programming mode ( par /ser = v dd ), sdi can be used to power down the part. sdi can be driven with 1.8v to 3.3v logic. gnd ( pins 22, 45, 49, exposed pad pin 53): adc power ground. the exposed pad must be soldered to the pcb ground. ognd (pin 33): output driver ground. must be shorted to the ground plane by a very low inductance path. use multiple vias close to the pin. ov dd (pin 34): output driver supply. bypass to ground with a 0.1f ceramic capacitor. sdo ( pin 46): in serial programming mode ( par / ser = 0 v ), sdo is the optional serial interface data output . data on sdo is read back from the mode control registers and can be latched on the falling edge of sck. sdo is an open- drain n- channel mosfet output that requires an external 2 k pull- up resistor of 1.8 v to 3.3v . if read- back from the mode control registers is not needed, the pull- up resistor is not necessary and sdo can be left unconnected. in parallel programming mode ( par / ser = v dd ), sdo is an input that enables internal 100? termination resistors on the digital outputs. when used as an input, sdo can be driven with 1.8 v to 3.3 v logic through a 1 k series resistor. p in func t ions
ltc2172-14/ ltc2171-14/ltc2170-14 18 21721014fb p in func t ions par /ser (pin 47): programming mode selection pin. connect to ground to enable serial programming mode. cs , sck, sdi and sdo become a serial interface that con- trols the a/d operating modes. connect to v dd to enable parallel programming mode where cs , sck, sdi and sdo become parallel logic inputs that control a reduced set of the a/d operating modes. par /ser should be connected directly to ground or the v dd of the part and not be driven by a logic signal. v ref ( pin 48): reference voltage output. bypass to ground with a 1f ceramic capacitor, nominally 1.25v. sense (pin 50): reference programming pin. connect- ing sense to v dd selects the internal reference and a 1v input range. connecting sense to ground selects the internal reference and a 0.5 v input range. an external reference between 0.625 v and 1.3 v applied to sense selects an input range of 0.8 ? v sense . lvds o utputs the following pins are differential lvds outputs. the output current level is programmable. there is an op- tional internal 100? termination resistor between the pins of each lvds output pair. out 4b C / out 4b + , out 4a C / out 4a + ( pins 23/24, pins 25/ 26): serial data outputs for channel 4. in 1-lane output mode, only out4a C /out4a + are used. out 3b C / out 3b + , out 3a C / out 3a + ( pins 27/28, pins 29/30): serial data outputs for channel 3. in 1-lane output mode, only out3a C /out3a + are used. fr C /fr + (pin 31/pin 32): frame start output. dco C /dco + (pin 35/pin 36): data clock output. out 2b C / out 2b + , out 2a C / out 2a + ( pins 37/38, pins 39/40): serial data outputs for channel 2. in 1-lane output mode, only out2a C /out2a + are used. out 1b C / out 1b + , out 1a C / out 1a + ( pins 41/42, pins 43/44): serial data outputs for channel 1. in 1-lane output mode, only out1a C /out1a + are used.
ltc2172-14/ ltc2171-14/ltc2170-14 19 21721014fb func t ional b lock diagra m pll data serializer sample- and-hold 14-bit adc core channel 1 analog input 14-bit adc core channel 2 analog input 14-bit adc core channel 3 analog input 14-bit adc core channel 4 analog input 1.8v v dd 1.8v enc + enc ? ov dd v dd /2 diff ref amp ref buf 2.2f 0.1f 0.1f 0.1f refh refl range select 1.25v reference refh refl out1a out1b out2a out2b out3a out3b out4a out4b data clockout frame ognd vcm12 gnd vcm34 0.1f 0.1f sdo cs sense v ref 1f mode control registers sck par/ ser sdi 217214 f01 sample- and-hold sample- and-hold sample- and-hold figure 1. functional block diagram
ltc2172-14/ ltc2171-14/ltc2170-14 20 21721014fb converter operation the ltc2172-14/ltc2171-14/ltc2170-14 are low power, 4-channel, 14-bit, 65 msps/40msps/25msps a/d convert- ers that are powered by a single 1.8 v supply. the analog inputs should be driven differentially. the encode input can be driven differentially for optimal jitter performance, or single-ended for lower power consumption. the digital outputs are serial lvds to minimize the number of data lines. each channel outputs two bits at a time (2-lane mode) or one bit at a time (1- lane mode). many additional features can be chosen by programming the mode control registers through a serial spi port. analog input the analog inputs are differential cmos sample-and-hold circuits (figure 2). the inputs should be driven differen- tially around a common mode voltage set by the v cm12 a pplica t ions i n f or m a t ion or v cm34 output pins, which are nominally v dd /2. for the 2v input range, the inputs should swing from v cm C 0.5 v to v cm + 0.5 v. there should be a 180 phase difference between the inputs. the four channels are simultaneously sampled by a shared encode circuit (figure 2). input drive circuits input filtering if possible, there should be an rc lowpass filter right at the analog inputs. this lowpass filter isolates the drive circuitry from the a/d sample-and-hold switch- ing and limits wideband noise from the drive circuitry. figure 3 shows an example of an input rc filter. the rc component values should be chosen based on the ap- plications input frequency. figure 2. equivalent input circuit. only one of the four analog channels is shown. figure 3. analog input circuit using a transformer. recommended for input frequencies from 5mhz to 70mhz c sample 3.5pf r on 25 r on 25 v dd v dd ltc2172-14 a in + 217214 f02 c sample 3.5pf v dd a in ? enc ? enc + 1.2v 10k 1.2v 10k c parasitic 1.8pf c parasitic 1.8pf 10 10 25 25 25 25 50 0.1f a in + a in ? 12pf 0.1f v cm ltc2172-14 analog input 0.1f t1 1:1 t1: ma/com mabaes0060 resistors, capacitors are 0402 package size 217214 f03
ltc2172-14/ ltc2171-14/ltc2170-14 21 21721014fb transformer coupled circuits figure 3 shows the analog input being driven by an rf transformer with a center-tapped secondary. the center tap is biased with v cm , setting the a/d input at its opti- mal dc level. at higher input frequencies a transmission line balun transformer (figures 4 to 6) has better balance, resulting in lower a/d distortion. a pplica t ions i n f or m a t ion amplifier circuits figure 7 shows the analog input being driven by a high speed differential amplifier . the output of the amplifier is ac-coupled to the a/d so the amplifiers output common mode voltage can be optimally set to minimize distortion. at very high frequencies an rf gain block will often have lower distortion than a differential amplifier. if the gain block is single-ended, then a transformer circuit (figures 4 to 6) should convert the signal to differential before driving the a/d. figure 5. recommended front-end circuit for input frequencies from 170mhz to 300mhz figure 6. recommended front-end circuit for input frequencies above 300mhz figure 4. recommended front-end circuit for input frequencies from 70mhz to 170mhz 25 25 50 0.1f a in + a in ? 4.7pf 0.1f v cm analog input 0.1f 0.1f t1 t2 t1: ma/com maba-007159-000000 t2: ma/com mabaes0060 resistors, capacitors are 0402 package size 217214 f04 ltc2172-14 25 25 50 0.1f a in + a in ? 1.8pf 0.1f v cm analog input 0.1f 0.1f t1 t2 t1: ma/com maba-007159-000000 t2: coilcraft wbc1-1lb resistors, capacitors are 0402 package size 217214 f05 ltc2172-14 25 25 50 0.1f 2.7nh 2.7nh a in + a in ? 0.1f v cm analog input 0.1f 0.1f t1 t1: ma/com etc1-1-13 resistors, capacitors are 0402 package size 217214 f06 ltc2172-14 25 25 200 200 0.1f a in + a in ? 12pf 0.1f v cm ltc2172-14 217214 f07 ? ? + + analog input high speed differential amplifier 0.1f figure 7. front-end circuit using a high speed differential amplifier
ltc2172-14/ ltc2171-14/ltc2170-14 22 21721014fb a pplica t ions i n f or m a t ion reference the ltc2172-14/ltc2171-14/ltc2170-14 has an internal 1.25v voltage reference. for a 2 v input range using the internal reference, connect sense to v dd . for a 1 v input range using the internal reference, connect sense to ground. for a 2 v input range with an external reference, apply a 1.25v reference voltage to sense (figure 9). the input range can be adjusted by applying a voltage to sense that is between 0.625 v and 1.30 v. the input range will then be 1.6 ? v sense . the reference is shared by all four adc channels, so it is not possible to independently adjust the input range of individual channels. the v ref , refh and refl pins should be bypassed, as shown in figure 8. the 0.1 f capacitor between refh and refl should be as close to the pins as possible ( not on the backside of the circuit board). encode input the signal quality of the encode inputs strongly affects the a/d noise performance. the encode inputs should be treated as analog signalsdo not route them next to digital traces on the circuit board. there are two modes of operation for the encode inputs: the differential encode mode (figure 10), and the single-ended encode mode (figure 11). figure 8. reference circuit figure 9. using an external 1.25v reference figure 10. equivalent encode input circuit for differential encode mode figure 11. equivalent encode input circuit for single-ended encode mode v ref refh sense tie to v dd for 2v range; tie to gnd for 1v range; range = 1.6 ? v sense for 0.625v < v sense < 1.300v 1.25v refl 0.1f 2.2f internal adc high reference buffer 5 0.8x diff amp internal adc low reference 1.25v bandgap reference 0.625v range detect and control 1f 0.1f 0.1f ltc2172-14 217214 f08 sense 1.25v external reference 1f 1f v ref 217214 f09 ltc2172-14 v dd ltc2172-14 217214 f10 enc ? enc + 15k v dd differential comparator 30k 30k enc + enc ? 217214 f11 0v 1.8v to 3.3v ltc2172-14 cmos logic buffer
ltc2172-14/ ltc2171-14/ltc2170-14 23 21721014fb the differential encode mode is recommended for sinu- soidal, pecl, or lvds encode inputs (figures 12 and 13). the encode inputs are internally biased to 1.2 v through 10k equivalent resistance. the encode inputs can be taken above v dd ( up to 3.6 v), and the common mode range is from 1.1 v to 1.6 v. in the differential encode mode, enc C should stay at least 200 mv above ground to avoid falsely triggering the single-ended encode mode. for good jitter performance enc + should have fast rise and fall times. the single-ended encode mode should be used with cmos encode inputs. to select this mode, enc C is con- nected to ground and enc + is driven with a square wave encode input. enc + can be taken above v dd ( up to 3.6v) so 1.8 v to 3.3 v cmos logic levels can be used. the enc + threshold is 0.9 v . for good jitter performance enc + should have fast rise and fall times. clock pll and duty cycle stabilizer the encode clock is multiplied by an internal phase-locked loop ( pll) to generate the serial digital output data. if the encode signal changes frequency or is turned off, the pll requires 25s to lock onto the input clock. a clock duty cycle stabilizer circuit allows the duty cycle of the applied encode signal to vary from 30% to 70%. in the serial programming mode it is possible to disable a pplica t ions i n f or m a t ion the duty cycle stabilizer, but this is not recommended. in the parallel programming mode the duty cycle stabilizer is always enabled. digital outputs the digital outputs of the ltc2172-14/ltc2171-14/ ltc2170-14 are serialized lvds signals. each chan- nel outputs two bits at a time (2-lane mode) or one bit at a time (1-lane mode). the data can be serialized with 16-, 14-, or 12-bit serialization ( see the timing diagrams section for details). note that with 12-bit serialization the two lsbs are not available this mode is included for compatibility with the 12-bit versions of these parts. the output data should be latched on the rising and falling edges of the data clockout ( dco). a data frame output ( fr) can be used to determine when the data from a new conversion result begins. in the 2-lane, 14- bit serialization mode, the frequency of the fr output is halved. the maximum serial data rate for the data outputs is 1gbps, so the maximum sample rate of the adc will de - pend on the serialization mode as well as the speed grade of the adc ( see table 1). the minimum sample rate for all serialization modes is 5msps. figure 12. sinusoidal encode drive figure 13. pecl or lvds encode drive 50 100 0.1f 0.1f 0.1f t1 t1 = ma/com etc1-1-13 resistors and capacitors are 0402 package size 50 ltc2172-14 217214 f12 enc ? enc + enc + enc ? pecl or lvds clock 0.1f 0.1f 217214 f13 ltc2172-14
ltc2172-14/ ltc2171-14/ltc2170-14 24 21721014fb a pplica t ions i n f or m a t ion by default the outputs are standard lvds levels: a 3.5ma output current and a 1.25 v output common mode volt- age. an external 100? differential termination resistor is required for each lvds output pair. the termination resistors should be located as close as possible to the lvds receiver. the outputs are powered by ov dd and ognd which are isolated from the a/d core power and ground. programmable lvds output current the default output driver current is 3.5 ma. this current can be adjusted by control register a2 in serial programming mode. available current levels are 1.75ma, 2.1ma, 2.5ma, 3ma, 3.5ma, 4 ma and 4.5 ma. in parallel programming mode the sck pin can select either 3.5ma or 1.75ma. optional lvds driver internal termination in most cases, using just an external 100? termination resistor will give excellent lvds signal integrity. in addi- tion, an optional internal 100? termination resistor can be enabled by serially programming mode control register a2. the internal termination helps absorb any reflections caused by imperfect termination at the receiver. when the internal termination is enabled, the output driver current is doubled to maintain the same output voltage swing. in parallel programming mode the sdo pin enables internal termination. internal termination should only be used with 1.75ma, 2.1ma or 2.5ma l vds output current modes. table 1. maximum sampling frequency for all serialization modes. note that these limits are for the ltc2172-14. the sampling frequency for the slower speed grades cannot exceed 40mhz (ltc2171-14) or 25mhz (ltc2170-14). serialization mode maximum sampling frequency, f s (mhz) dco frequency fr frequency serial d ata rate 2-lane 16-bit serialization 65 4 ? f s f s 8 ? f s 2-lane 14-bit serialization 65 3.5 ? f s 0.5 ? f s 7 ? f s 2-lane 12-bit serialization 65 3 ? f s f s 6 ? f s 1-lane 16-bit serialization 62.5 8 ? f s f s 16 ? f s 1-lane 14-bit serialization 65 7 ? f s f s 14 ? f s 1-lane 12-bit serialization 65 6 ? f s f s 12 ? f s d ata format table 2 shows the relationship between the analog input voltage and the digital data output bits. by default the output data format is offset binary. the 2 s complement format can be selected by serially programming mode control register a1. table 2. output codes vs input voltage a in + C a in C (2v range) d13-d0 (offset binary) d13-d0 (2s complement) >1.000000v +0.999878v +0.999756v 11 1111 1111 1111 11 1111 1111 1111 11 1111 1111 1110 01 1111 1111 1111 01 1111 1111 1111 01 1111 1111 1110 +0.000122v +0.000000v C0.000122v C0.000244v 10 0000 0000 0001 10 0000 0000 0000 01 1111 1111 1111 01 1111 1111 1110 00 0000 0000 0001 00 0000 0000 0000 11 1111 1111 1111 11 1111 1111 1110 C0.999878v C1.000000v ?C1.000000v 00 0000 0000 0001 00 0000 0000 0000 00 0000 0000 0000 10 0000 0000 0001 10 0000 0000 0000 10 0000 0000 0000 digital output randomizer interference from the a/d digital outputs is sometimes unavoidable. digital interference may be from capacitive or inductive coupling or coupling through the ground plane. even a tiny coupling factor can cause unwanted tones in the adc output spectrum. these unwanted tones can be randomized by randomizing the digital output before it is transmitted off chip, which reduces the unwanted tone amplitude. the digital output is randomized by applying an exclu- sive-or logic operation between the lsb and all other data output bits. to decode, the reverse operation is
ltc2172-14/ ltc2171-14/ltc2170-14 25 21721014fb appliedan exclusive-or operation is applied between the lsb and all other bits. the fr and dco outputs are not affected. the output randomizer is enabled by serially programming mode control register a1. digital output test pattern to allow in-circuit testing of the digital interface to the a/d, there is a test mode that forces the a/d data outputs (d13-d0) of all channels to known values. the digital output test patterns are enabled by serially programming mode control registers a3 and a4. when enabled, the test patterns override all other formatting modes : 2 s comple- ment and randomizer. output disable the digital outputs may be disabled by serially program- ming mode control register a2. the current drive for all digital outputs, including dco and fr, are disabled to save power or enable in - circuit testing. when disabled, the com - mon mode of each output pair becomes high impedance, but the differential impedance may remain low. sleep and nap modes the a/d may be placed in sleep or nap modes to conserve power. in sleep mode the entire chip is powered down, resulting in 1 mw power consumption. sleep mode is enabled by mode control register a 1 ( serial program - ming mode), or by sdi ( parallel programming mode). the amount of time required to recover from sleep mode depends on the size of the bypass capacitors on v ref , refh and refl. for the suggested values in figure 8, the a/d will stabilize after 2ms. in nap mode any combination of a/d channels can be powered down while the internal reference circuits and the pll stay active, allowing a faster wake-up than from sleep mode. recovering from nap mode requires at least 100 clock cycles. if the application demands very accurate dc settling, then an additional 50 s should be allowed so the on-chip references can settle from the slight temperature shift caused by the change in supply current as the a/d leaves nap mode. nap mode is enabled by the mode control register a1 in the serial programming mode. a pplica t ions i n f or m a t ion device programming modes the operating modes of the ltc2172-14/ltc2171-14/ ltc2170-14 can be programmed by either a parallel interface or a simple serial interface. the serial interface has more flexibility and can program all available modes. the parallel interface is more limited and can only program some of the more commonly used modes. parallel programming mode to use the parallel programming mode, par /ser should be tied to v dd . the cs , sck, sdi and sdo pins are binary logic inputs that set certain operating modes. these pins can be tied to v dd or ground, or driven by 1.8 v, 2.5 v or 3.3v cmos logic. when used as an input, sdo should be driven through a 1 k series resistor. table 3 shows the modes set by cs, sck, sdi and sdo. table 3. parallel programming mode control bits ( par / ser = v dd ) pin description cs 2-lane/1-lane selection bit 0 = 2-lane, 16-bit serialization output mode 1 = 1-lane, 14-bit serialization output mode sck lvds current selection bit 0 = 3.5ma lvds current mode 1 = 1.75ma lvds current mode sdi power down control bit 0 = normal operation 1 = sleep mode sdo internal 100 termination selection bit 0 = internal termination disabled 1 = internal termination enabled serial programming mode to use the serial programming mode, par /ser should be tied to ground. the cs , sck, sdi and sdo pins become a serial interface that program the a/d mode control registers. data is written to a register with a 16- bit serial word. data can also be read back from a register to verify its contents. serial data transfer starts when cs is taken low. the data on the sdi pin is latched at the first 16 rising edges of sck. any sck rising edges after the first 16 are ignored. the data transfer ends when cs is taken high again.
ltc2172-14/ ltc2171-14/ltc2170-14 26 21721014fb a pplica t ions i n f or m a t ion the first bit of the 16- bit input word is the r/w bit. the next seven bits are the address of the register (a6:a0). the final eight bits are the register data (d7:d0). if the r/ w bit is low, the serial data ( d 7:d 0) will be written to the register set by the address bits ( a 6:a 0). if the r/ w bit is high, data in the register set by the address bits ( a 6:a 0) will be read back on the sdo pin ( see the timing diagrams section). during a readback command the register is not updated and data on sdi is ignored. the sdo pin is an open-drain output that pulls to ground with a 200? impedance. if register data is read back through sdo, an external 2k pull-up resistor is required. if serial data is only written and readback is not needed, then sdo can be left floating and no pull-up resistor is needed. table 4 shows a map of the mode control registers. software reset if serial programming is used, the mode control registers should be programmed as soon as possible after the power supplies turn on and are stable. the first serial command must be a software reset which will reset all register data bits to logic 0. to perform a software reset, bit d7 in the reset register is written with a logic 1. after the reset spi write command is complete, bit d7 is automatically set back to zero. table 4. serial programming mode register map ( par /ser = gnd) register a0: reset register (address 00h) d7 d6 d5 d4 d3 d2 d1 d0 reset x x x x x x x bit 7 reset software reset bit 0 = not used 1 = software reset. all mode control registers are reset to 00h. the adc is momentarily placed in sleep mode. this bit is automatically set back to zero after the reset is complete at the end of the spi write command. the reset register is write only. bits 6-0 unused, dont care bits. register a1: power-down register (address 01h) d7 d6 d5 d4 d3 d2 d1 d0 dcsoff rand twoscomp sleep nap_4 nap_3 nap_2 nap_1 bit 7 dcsoff clock duty cycle stabilizer bit 0 = clock duty cycle stabilizer on 1 = clock duty cycle stabilizer off. this is not recommended. bit 6 rand data output randomizer mode control bit 0 = data output randomizer mode off 1 = data output randomizer mode on bit 5 t woscomp tw o s complement mode control bit 0 = offset binar y data format 1 = tw o s complement data format bits 4-0 sleep:nap_4:nap_1 sleep/nap mode control bits 00000 = normal operation 0xxx1 = channel 1 in nap mode 0xx1x = channel 2 in nap mode 0x1xx = channel 3 in nap mode 01xxx = channel 4 in nap mode 1xxxx = sleep mode. all channels are disabled note: any combination of channels can be placed in nap mode.
ltc2172-14/ ltc2171-14/ltc2170-14 27 21721014fb a pplica t ions i n f or m a t ion register a2: output mode register (address 02h) d7 d6 d5 d4 d3 d2 d1 d0 ilvds2 ilvds1 ilvds0 termon outoff outmode2 outmode1 outmode0 bits 7-5 ilvds2:ilvds0 lvds output current bits 000 = 3.5ma l vds output driver current 001 = 4.0ma lvds output driver current 010 = 4.5ma lvds output driver current 011 = not used 100 = 3.0ma lvds output driver current 101 = 2.5ma lvds output driver current 110 = 2.1ma lvds output driver current 111 = 1.75ma lvds output driver current bit 4 termon lvds internal t ermination bit 0 = internal termination off 1 = internal termination on. lvds output driver current is 2x the current set by ilvds2:ilvds0. internal termination should only be used with 1.75ma, 2.1ma or 2.5ma lvds output current modes. bit 3 outoff output disable bit 0 = digital outputs are enabled. 1 = digital outputs are disabled. bits 2-0 outmode2:outmode0 digital output mode control bits 000 = 2-lanes, 16-bit serialization 001 = 2-lanes, 14-bit serialization 010 = 2-lanes, 12-bit serialization 011 = not used 100 = not used 101 = 1-lane, 14-bit serialization 110 = 1-lane, 12-bit serialization 111 = 1-lane, 16-bit serialization register a3: test pattern msb register (address 03h) d7 d6 d5 d4 d3 d2 d1 d0 outtest x tp13 tp12 tp11 tp10 tp9 tp8 bit 7 outtest digital output t est pattern control bit 0 = digital output test pattern off 1 = digital output test pattern on bit 6 unused, dont care bit. bits 5-0 tp13:tp8 test pattern data bits (msb) tp13:tp8 set the t est pattern for data bit 13 (msb) through data bit 8. register a4: test pattern lsb register (address 04h) d7 d6 d5 d4 d3 d2 d1 d0 tp7 tp6 tp5 tp4 tp3 tp2 tp1 tp0 bits 7-0 tp7:tp0 test pattern data bits (lsb) tp7:tp0 set the t est pattern for data bit 7 through data bit 0 (lsb).
ltc2172-14/ ltc2171-14/ltc2170-14 28 21721014fb a pplica t ions i n f or m a t ion grounding and bypassing the ltc2172-14/ltc2171-14/ltc2170-14 requires a printed circuit board with a clean unbroken ground plane. a multilayer board with an internal ground plane in the first layer beneath the adc is recommended. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. high quality ceramic bypass capacitors should be used at the v dd , ov dd , v cm , v ref , refh and refl pins. bypass capacitors must be located as close to the pins as possible. of particular importance is the 0.1 f capacitor between refh and refl. this capacitor should be on the same side of the circuit board as the a/d, and as close to the device as possible (1.5 mm or less). size 0402 ceramic capacitors are recommended. the larger 2.2 f capacitor between refh and refl can be somewhat further away. the traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. the analog inputs, encode signals and digital outputs should not be routed next to each other. ground fill and grounded vias should be used as barriers to isolate these signals from each other. heat transfer most of the heat generated by the ltc2172-14/ltc2171-14/ ltc2170-14 is transferred from the die through the bottom- side exposed pad and package leads onto the printed circuit board. for good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the pc board. this pad should be connected to the internal ground planes by an array of vias.
ltc2172-14/ ltc2171-14/ltc2170-14 29 21721014fb typical a pplica t ions silkscreen top top side inner layer 2 gnd inner layer 3
ltc2172-14/ ltc2171-14/ltc2170-14 30 21721014fb t ypical a pplica t ions inner layer 4 inner layer 5 power bottom side silkscreen bottom
ltc2172-14/ ltc2171-14/ltc2170-14 31 21721014fb t ypical a pplica t ions ltc2172 8 7 6 5 4 3 2 1 a in1 + a in1 ? v cm12 a in2 + a in2 ? refh refh refl refl a in3 + a in3 ? v cm34 a in4 + a in4 ? out2a + out2a ? out2b + out2b ? dco + dco ? ov dd ognd fr + fr ? out3a + out3a ? out3b + out3b ? 9 10 11 12 13 14 33 34 35 36 37 38 39 40 32 31 30 29 28 27 v dd v dd enc + enc ? cs sck sdi gnd out4b ? out4b + out4a ? out4a + 1615 v dd 17 18 19 20 21 22 23 24 25 26 v dd v dd sense gnd v ref par/ ser sdo gnd out1a + out1a ? out1b + out1b ? 5152 50 49 48 sdo par/ ser sense 47 46 45 44 43 42 41 c30 0.1f c1 2.2f c59 0.1f c3 0.1f c2 0.1f c29 0.1f c7 0.1f spi bus digital outputs ov dd c46 0.1f c47 0.1f a in1 a in1 a in2 a in2 a in3 a in3 a in4 a in4 encode clock encode clock 217214 ta02 r14 1k digital outputs c16 0.1f c4 1f c5 1f v dd c17 1f ltc2172 schematic
ltc2172-14/ ltc2171-14/ltc2170-14 32 21721014fb p ackage descrip t ion ukg package 52-lead plastic qfn (7mm 8mm) (reference ltc dwg # 05-08-1729 rev ?) 7.00 0.10 (2 sides) note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (see note 6) pin 1 notch r = 0.30 typ or 0.35 45c chamfer 0.40 0.10 5251 1 2 bottom view?exposed pad top view side view 6.50 ref (2 sides) 8.00 0.10 (2 sides) 5.50 ref (2 sides) 0.75 0.05 0.75 0.05 r = 0.115 typ r = 0.10 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 6.45 0.10 5.41 0.10 0.00 ? 0.05 (ukg52) qfn rev ? 0306 5.50 ref (2 sides) 5.41 0.05 6.45 0.05 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 6.10 0.05 7.50 0.05 6.50 ref (2 sides) 7.10 0.05 8.50 0.05 0.25 0.05 0.50 bsc package outline
ltc2172-14/ ltc2171-14/ltc2170-14 33 21721014fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 03/10 changed sampling frequency max for ltc2171-14 from 45mhz to 40mhz in the timing characteristics section. 6 added full part numbers to grounding and bypassing and heat transfer sections in applications information. 28 revised descriptions and comments in the related parts section. 34 b 07/11 corrected pin names for pins 41-44 in the pin functions section. 18 revised software reset paragraph and table 4 in the applications information section. 26
ltc2172-14/ ltc2171-14/ltc2170-14 34 21721014fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com lt 0711 rev b ? printed in usa ? linear technology corporation 2010 r ela t e d p ar t s part number description comments adcs ltc2170-12/ltc2171- 12/ltc2172-12 12-bit, 25msps/40msps/65msps 1.8v quad adcs, ultralow power 160mw/198mw/306mw, 71db snr, 90db sfdr, serial lvds outputs, 7mm 8mm qfn-52 ltc2173-12/ltc2174- 12/ltc2175-12 12-bit, 80msps/105msps/125msps 1.8v quad adcs, ultralow power 369mw/439mw/545mw, 70.6db snr, 88db sfdr, serial lvds outputs, 7mm 8mm qfn-52 ltc2256-14/ltc2257- 14/ltc2258-14 14-bit, 25msps/40msps/65msps 1.8v adcs, ultralow power 35mw/49mw/81mw, 74db snr, 88db sfdr, ddr lvds/ddr cmos/cmos outputs, 6mm 6mm qfn-40 ltc2259-14/ltc2260- 14/ltc2261-14 14-bit, 80msps/105msps/125msps 1.8v adcs, ultralow power 89mw/106mw/127mw, 73.4db snr, 85db sfdr, ddr lvds/ddr cmos/cmos outputs, 6mm 6mm qfn-40 ltc2262-14 14-bit, 150msps 1.8 v adc, ultralow power 149mw, 72.8db snr, 88db sfdr, ddr lvds/ddr cmos/cmos outputs, 6mm 6mm qfn-40 ltc2263-14/ltc2264- 14/ltc2265-14 14-bit, 25msps/40msps/65msps 1.8v dual adcs, ultralow power 94mw/113mw/171mw, 73.7db snr, 90db sfdr, serial lvds outputs, 6mm 6mm qfn-40 ltc2263-12/ltc2264- 12/ltc2265-12 12-bit, 25msps/40msps/65msps 1.8v dual adcs, ultralow power 94mw/112mw/167mw, 71db snr, 90db sfdr, serial lvds outputs, 6mm 6mm qfn-40 ltc2266-14/ltc2267- 14/ltc2268-14 14-bit, 80msps/105msps/125msps 1.8v dual adcs, ultralow power 203mw/243mw/299mw, 73.1db snr, 88db sfdr, serial lvds outputs, 6mm 6mm qfn-40 ltc2266-12/ltc2267- 12/ltc2268-12 12-bit, 80msps/105msps/125msps 1.8v dual adcs, ultralow power 200mw/238mw/292mw, 70.6db snr, 88db sfdr, serial lvds outputs, 6mm 6mm qfn-40 rf mixers/demodulators ltc5517 40mhz to 900mhz direct conversion quadrature demodulator high iip3: 21dbm at 800mhz, integrated lo quadrature generator ltc5527 400mhz to 3.7ghz high linearity downconverting mixer 24.5dbm iip3 at 900mhz, 23.5dbm iip3 at 1900mhz, nf = 12.5db, 50 single-ended rf and lo ports, 5v supply ltc5557 400mhz to 3.8ghz high linearity downconverting mixer 24.7dbm iip3 at 1950mhz, 23.7dbm iip3 at 2.6ghz, nf = 13.2db, 3.3v supply operation, integrated transformer ltc5575 800mhz to 2.7ghz direct conversion quadrature demodulator high iip3: 28dbm at 900mhz, integrated lo quadrature generator, integrated rf and lo transformer amplifiers/filters ltc6412 800mhz, 31db range, analog-controlled variable gain amplifier continuously adjustable gain control, 35dbm oip3 at 240mhz, 10db noise figure, 4mm 4mm qfn-24 ltc6420-20 dual low noise, low distortion differential adc drivers for 300mhz if fixed gain 10v/v, 2.2nv/ hz total input referred noise, 80ma supply current per amplifier, 46dbm oip3 at 100mhz, 3mm 4mm qfn-20 ltc6421-20 dual low noise, low distortion differential adc drivers for 140mhz if fixed gain 10v/v, 2.2nv/hz total input referred noise, 40ma supply current per amplifier, 42dbm oip3 at 100mhz, 3mm 4mm qfn-20 ltc6605-7/ ltc6605-10/ ltc6605-14 dual matched 7mhz/10mhz/14mhz filters with adc drivers dual matched 2nd order lowpass filters with differential drivers, pin-programmable gain, 6mm 3mm dfn-22 signal chain receivers ltm9002 14-bit dual channel if/baseband receiver subsystem integrated high speed adc, passive filters and fixed gain differential amplifiers

▲Up To Search▲

Price & Availability of LTC2170IUKG-14PBF

	To Download LTC2170IUKG-14PBF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .